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a 400 msps 14-bit, 1.8v cmos direct digital synthesizer preliminary technical data AD9951 rev. prb information furnished by analog dev i ces is believ ed to be accurate and reliable. how e v e r, no responsibility is assumed by analog dev i ces for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherw i se under any patent or patent rights of analog dev i ces. trademarks and registered trademarks are the property of their respectiv e companies. one technol ogy way , p. o. box 9106, nor w ood, m a 02062-9106, u. s. a . tel : 781/ 329-4700 www.anal og.com fax: 781/326-8703 ? 2003 a n alog dev i ces, inc. a ll rights reserv e d. features 400 msps internal clock speed in teg r ated 14-b i t d/a co n v erter pro g r ammab l e p h ase/amp litu d e d i th erin g 3 2 - bit tuning word ph ase no ise < = 125 d b c/hz @ 1khz o ffset (da c o u t p u t) excellen t dy n a mic perfo rman ce 80d b sf dr @ 130mhz (+ /- 100khz offset) a o u t serial i/o control 1 . 8 v pow e r supply softw a r e a nd ha rdw a re c ontrolle d pow e r dow n 48-lead epa d-t q f p p ackag e support for 5 v input le v e ls on mos t digita l inputs pll refclk multiplier (4x to 20x) internal oscillator, can be driv en by a single cry s tal phase modulation capability multi-chip synchronization applications a g ile l.o. frequency sy nthesis fm chirp sourc e for ra da r a nd sc a nning sy s t e m s t est an d measu remen t eq u i p m en t functional block diagram da c dac i - set aout aout s y s t em c l oc k ti mi n g & control lo gi c i/ o updat e ref c lk sy n c out io port c o nt rol regis t er s sy n c reset m u x 4x -20 x cloc k m u l t ip le r s y s t em c l oc k refc lk o s c illa t o r/ b u f f e r sy n c 0 4 m u x p h ase a ccum u lat o r cos ( x) pha s e offs et dds cor e 19 z -1 z -1 os k pwrd wn 32 32 14 32 cryst al out en a b l e 14 p h as e a ccum u l a tor r e s et f r equ e n cy t u nin g wo r d dd s c l o c k
preliminary technical data AD9951 rev. prb 1/31/03 page 2 analog devices, inc. general description the AD9951 is a direct digital synthesizer (dds) featuring a 14-bit dac operating up to 400msps. the AD9951 uses advanced dds technology, coupled with an internal high-speed, high performance d/a converter to form a digitally- programmable, complete high-fre quency synthesizer capable of generating a frequency-agile anal og output sinusoidal waveform at up to 200 mhz. the AD9951 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). the frequency tuning and control words are loaded into the AD9951 via a serial i/o port. the AD9951 is specified to operate over the extended industrial temperature range of -40 to +85c. absolute maximum ratings 1 maximum junction temp. ............................. +150 c storage temperatu re ................................... -65 c to +1 50 c vs ............................................................................ +4 v operating temp. ........................... ................. -40 c to +85 c digital input voltage ............................... -0.7 v to +vs lead temp. ( 10 sec. soldering) ............................. ...... +300 c digital output current ....................................... 5 ma t ja ............................................................................. tbd c/w t jc tbd c/w * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. contents functional block diagram 1 general description 2 AD9951 preliminary electrical specifications 4 AD9951 pinmap 7 pin name 8 i/o 8 theory of operation 10 component blocks 10 dds core 10 phase truncation 11 clock input 11 phase locked loop (pll) 12 dac output 12 serial io port 13 register maps and descriptions 13 AD9951 register map 14 default 14 control register bit descriptions 15 control function register #1 (cfr1) 15 control function register #1 (cfr2) 19 other register descriptions 20 amplitude scale factor (asf) 20 amplitude ramp rate (arr) 20 frequency tuning word 0 (ftw0) 20 phase offset word (pow) 20
preliminary technical data AD9951 frequency tuning word 1 (ftw1) error! bookmark not defined. mode of operation 20 single tone mode 21 continuous clear and ?clear and releas e? phase accum u lator clear functions 21 continuous clear bits 21 clear and release function 21 program m i ng AD9951 features 21 phase offset control 21 phase/am plitude dithering 21 shaped on-off keying 22 auto shaped on-off keying m ode operation: 23 osk ramp rate timer 24 external shaped on-off keying m ode operation: 24 synchronization; register updates (i/o update) 25 functionality of the syncclk and i/o update 25 figure d- i/o synchroni zation block diagram 26 figure e - i/o synchroni zation tim i ng diagram 26 synchronizing multiple AD9951s error! bookmark not defined. using a single crystal to dr ive multiple AD9951 clock inputs error! bookmark not defined. serial port operation 28 instruction byte 29 serial interface port pin description 30 msb/lsb transfers 30 example operation 31 notes on serial port operation 31 power down functions of the AD9951 31 digital and input clock power down 32 AD9951 application suggestions 33 rev . p r b 1/31/03 page 3 analog devices , inc.
preliminary technical data AD9951 AD9951 preliminary electrical specifications (unless otherwise noted: (v s =+1.8 v r 5% , r set =1.96 k : , external reference clock frequency = 20 mhz with refclk multiplier ena b led a t 2 0 u ) param e t e r t e m p t e s t l e v e l a d 9 9 5 1 m i n typ m a x units ref clock input characteristics frequency range refclk multiplier disabled full vi 1 400 mhz refclk multiplier enabled at 4x full vi 20 100 mhz refclk multiplier enabled at 20x full vi 4 20 mhz input capacitance +25c v 3 pf input impedance +25c v 100 m : duty cy cle +25c v 50 % duty cy cle with refclk multiplier enabled +25c v 35 65 % dac output characteristics r e s o l u t i o n 1 4 b i t s full scale output current +25c 5 10 15 ma gain error +25c i -10 +10 %fs output offset +25c i 0.6 p a differential nonlinearity +25c v 1 lsb integral nonlinearity +25c v 2 lsb output capacitance +25c v 5 pf res i dual p h as e nois e @ 1 khz offs et, 40 m h z a out refclk multiplier enabled @ 20 u + 2 5 c v - 8 9 d b c / h z refclk multiplier enabled @ 4 u + 2 5 c v - 1 0 5 d b c / h z refclk multiplier disabled +25c v -116 dbc/hz voltage compliance range +25c i avdd- 0.375 a v d d + 0.25v v wideband sfdr: 1 ? 20 mhz analog out +25c v dbc 20 ? 40 mhz analog out +25c v dbc 40 ? 60 mhz analog out +25c v dbc 60 ? 80 mhz analog out +25c v dbc 80 ? 100 mhz analog out +25c v dbc 100 ? 120 mhz analog out +25c v dbc 120 ? 140 mhz analog out +25c v dbc 140 ? 160 mhz analog out +25c v dbc narrow band sfdr 10 mhz analog out (1 mhz) +25c v dbc 10 mhz analog out (250 khz) +25c v dbc 10 mhz analog out ( 50 khz) +25c v dbc 10 mhz analog out ( 10 khz) +25c v dbc 65 mhz analog out ( 1 mhz) +25c v dbc 65 mhz analog out ( 250 khz) +25c v dbc 65 mhz analog out ( 50 khz) +25c v dbc 65 mhz analog out ( 10 khz) +25c v dbc 80 mhz analog out ( 1 mhz) +25c v dbc 80 mhz analog out ( 250 khz) +25c v dbc 80 mhz analog out ( 50 khz) +25c v dbc 80 mhz analog out ( 10 khz) +25c v dbc 100 mhz analog out ( 1 mhz) +25c v dbc 100 mhz analog out ( 250 khz) +25c v dbc 100 mhz analog out ( 50 khz) +25c v dbc 100 mhz analog out ( 10 khz) +25c v dbc 120 mhz analog out ( 1 mhz) +25c v dbc 120 mhz analog out ( 250 khz) +25c v dbc 120 mhz analog out ( 50 khz) +25c v dbc 120 mhz analog out ( 10 khz) +25c v dbc 140 mhz analog out ( 1 mhz) +25c v dbc 140 mhz analog out ( 250 khz) +25c v dbc 140 mhz analog out ( 50 khz) +25c v dbc 140 mhz analog out ( 10 khz) +25c v dbc 160 mhz analog out ( 1 mhz) +25c v dbc 160 mhz analog out ( 250 khz) +25c v dbc rev . p r b 1/31/03 page 4 analog devices , inc.
preliminary technical data AD9951 rev. prb 1/31/03 page 5 analog devices, inc. parameter temp test min typ max units level 160 mhz analog out ( 50 khz) +25c v dbc 160mhz analog out ( 10 khz) +25c v dbc timing characteristics serial control bus maximum frequency minimum clock pulse width low (t pwl ) minimum clock pulse width high (t pwh ) maximum clock rise/fall time minimum data setup time (t ds ) minimum data hold time (t dh ) maximum data valid time (t dv ) wake-up time 2 minimum reset pulsewidth high (t rh ) full full full full full full full full full full iv iv iv iv iv iv iv iv iv iv 7 7 10 0 25 5 5 1 25 mhz ns ns ns ns ns ns ms sysclk cycles 3 cmos logic inputs logic ?1? voltage @ dvdd = 1.8v logic ?0? voltage @ dvdd = 1.8v logic ?1? voltage @ dvdd = 3.3v logic ?0? voltage @ dvdd = 3.3v logic ?1? current logic ?0? current input capacitance +25c +25c +25c +25c +25c +25c +25c i i i i v % % 3 tbd 12 12 v v p a p a pf cmos logic outputs (1ma load) logic ?1? voltage (include for both dvdd) logic ?0? voltage +25c +25c i i tbd 0.4 v v power supply +vs current full operating conditions 400 mhz clock 120 mhz clock power-down mode full-sleep mode +25c +25c +25c +25c +25c +25c i i i i i i 30 tbd tbd tbd tbd tbd ma ma ma ma ma ma notes 1 absolute maximum ratings are limiting values to be applied i ndividually, and be yond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time affect device reliability. 2 wake-up time refers to recovery from analog power down mode s (see power down modes of operation). the longest time required is for the reference clock multiplier pll to lock up (if it is being used). the wake-up time assumes that there is no capacitor on dac_bp, and that the recomme nded pll loop filter values are used. 3 sysclk refers to the actual clock freque ncy used on-chip by the AD9951. if the reference clock multiplier is used to multiply the external reference frequency, then the sysclk frequency is the external frequency multiplied by the reference clock multiplier multiplication factor. if the reference clock multiplier is not used, then the sysclk frequency is the same as the external refclk frequency. specifications are subject to change without notice. explanation of test levels i ? 100% production tested. ii ? 100% production tested at +25 q c and sample tested at specified temperatures. iii ? sample tested only. iv ? parameter is guaranteed by design and characterization testing. v ? parameter is a typical value only. vi ? devices are 100% production tested at +25c and guaranteed by design and characterization testing for industrial operating temperature range.
preliminary technical data AD9951 ordering guide model temperature range package description package option AD9951asv -40c t o +85c 48-l ead qfp epad sv-48 AD9951pc b + 2 5 c eval uat i o n b o a r d caution esd (electrostatic discharge) s ensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge w i thout detection. although the AD9951 f eatures proprietary esd protection circuitry , permanent damage may occur on devices subjected to high-energy electrostatic discharges. t herefore, proper esd prec autions are recommended to avoid performance degradation or loss of functionality . rev . p r b 1/31/03 page 6 analog devices , inc.
preliminary technical data AD9951 AD9951 pinmap avd d os c/ r e f c l k os cb / r e f c l kb ag n d a d 9951 pi nout 48 leads 35 34 33 32 31 30 29 27 26 25 23 22 21 20 18 17 16 15 14 12 11 10 13 47 46 45 44 43 42 41 40 39 48 11 36 38 37 28 24 19 9 8 7 6 5 4 3 2 1 d a c b p d a c _ r s e t s y n c c l k dv dd i/o u p d a te d g n d d g n d o s k s c l k _ c s res e t s d i o d v d d _ i o dgnd s d o i o s y n c lo o p _f i l t e r dgnd dv dd d g n d pw r d w n c t l a g n d a v d d a v d d a g n d i o u t b i o u t a g n d a v d d c l km odes e l e ct cr y s t a l ou t ag n d ag n d nc avd d ag n d ag n d s y n c _ i n a g n d a v d d ag n d avd d avd d avd d figure 1 AD9951 pinmap rev . p r a 1/31/03 page 7 analog devices , inc.
preliminary technical data AD9951 hardw a re pin descriptions pin # pin name i/o description 1 i/o update i the rising edge transfers the contents of the internal buffer m e m o ry to the io registers. 2,34 dvdd i digital power supply pins. 3,33, 42, 47,48 dgnd i digital power ground pins. 4,6, 13,16,18,19, 25,27, 29 avdd i analog power supply pins. 5,7, 14,15, 17,22, 26,30, 31, 32 agnd i analog power ground pins. 8 oscb/refclkb i com p lem e ntary reference clock/oscillator input (400mhz m a x.). note: w h en the refclk port is operated in single-ended m ode, then refclkb should be decoupled to avdd with a 0.1 p f capacitor. 9 osc/refclk i reference clock/oscillator input (400 mhz m a x.). see clock input section of datasheet for details on the refclk/oscillator operation. 10 crystal out o output of the oscillator section. 11 clkmodeselect i control pin for the oscillator section. w h en high, the oscillator section is enabled. w h en low, the oscillator section is bypassed. 12 loop_filter i this pin provides the connection for the external zero com p ensation network of the refclk multiplier?s pll loop filter. the network consists of a 1k ohm resistor in series with a 0.1 p f capacitor tied to avdd. 20 ioutb o com p lem e ntary dac output. 2 1 i o u t o d a c o u t p u t . 23 dacbp i dac ?biasline? decoupling pin. 2 4 d a c _ r s e t i a resistor (3.85k : nom inal) connected from agnd to dac_rset establishes the ref e rence current f o r the dac. 28 nc x no connect, leave pin floating. 35 pwrdwnctl i input pin used as an external power down control. see the external power down control section of this docum ent for details. 36 reset i active high hardware reset pin. assertion of the reset pin forces the AD9951 to the initial state, as described in the io port register m a p. 3 7 i o s y n c i asynchronous active high reset of the serial port controller. when high, the current io operation is im m e diately term inated enabling a new io operation to commence once iosync is returned low rev . p r a 1/31/03 page 8 analog devices , inc.
preliminary technical data AD9951 3 8 s d o o when operating the i/o port as a 3-wire serial port this pin serves as the serial data output. when operated as a 2-wire serial port this pin is the unused and can be left unconnected. 3 9 c s - b a r i this pin functions as an active low chip select that allows multiple devices to share the io bus. 4 0 s c l k i this pin functions as the serial data clock for io operations 4 1 s d i o i / o when operating the i/o port as a 3-wire serial port this pin serves as the serial data input , only. when operated as a 2-wire serial port this pin is the bi- directional serial data pin. 43 dvdd_i/o i digital power supply (for io cells only, 3.3v optional) 4 4 s y n c _ i n i input signal used to synchronize multiple AD9951s. this input is connected to the sync_clk output of a different AD9951. 4 5 s y n c _ c l k o clock output pin, which serv es as a synchronizer for external hardware. 4 6 o s k i input pin used to control the direction of the shaped on-off keying function when program m e d for operation. osk is synchronous to the sync_clk pin. when osk is not pr ogram m e d, this pin should be tied to dgnd. table 1 hardware pin descriptions rev . p r a 1/31/03 page 9 analog devices , inc.
preliminary technical data AD9951 theory of operation component blocks dds core the output frequency (f o ) of the dds is a function of the frequency of system clock ( sysclk ), the value of the frequency tuning word (ftw ), and the capacity of the accumulator (2 32 , in this case). the exact relationship is given below with f s defined as the frequency of sysclk. f o = (ftw)(f s ) / 2 32 { 0 d ftw d 2 31 f o = f s* ( 1 ? ( ftw / 2 32 ) ) { 2 31 < ftw < 2 32 -1 the AD9951 frequency tuning word(s) are unsi gned num bers, where 80000000( hex) represents the highest output frequency possible, com m only re ferred to as the nyquist frequency. values ranging from than 80000001(hex) to ffffffff (hex) w ill be expressed as aliased frequencies less than nyquist. an example using a 3-bit phase ac cumulator will illustrate this principle. for a tuning word of 001, the phase accumulator output (p ao) increments from all zeros to all ones and repeats when the accumulator overfl ows after clock cycle number 8. for the tuning word of 111, the phase accumulator output (pao) decrements fro m all ones to all zeros and repeats when the accumulator overflows after clock cycle number 8. while the phase accumulator outputs are ?reversed? with respect to clock cycles, the outputs provide identical inputs to the phase to am plitude converter, which m e ans the dds output frequencies are identical. mathem atically, for a 3-bit accum ulator, the following equations apply: f o = f s* (ftw / 2 3 ) { 0 d ftw d 2 2 f o = f s* ( 1 ? ( ftw / 2 3 ) ) { 2 2 < ftw < 2 3 -1 for the 001 frequency tuning word: fout = fs * 1/2 3 = 1/8*fs and for t h e 111 frequency t uni ng word: fout = fs * (1 ? 7/8) = 1/8*fs the value at the output of the phase accumulator is translated to an amplitude value via the cos(x) functional block and routed to the dac. rev . p r a 1/31/03 page 10 analog devices , inc.
preliminary technical data AD9951 in certain applications it is desirable to force the output signal to zero phase. sim p ly setting the ftw to 0 does not accomplish this. it only results in the dds core holding its current phase value. thus, a control bit is required to for ce the phase accumulator output to zero. at power up the clear phase accumulator bit is set to logic one but the buffe r memory for this bit is cleared (logic zero). therefore, upon power up, the phase accumulator will remain clear until the first i/o update is issued. phase truncat i on the 32-bit phase values generated by the phase accu mulator are truncated to 19 bits prior to the cos(x) block. that is, the 19 m o st significant bits of phase are retained for subsequent processing. this is typical of standard dds architecture and is a trade off between hardware com p lexity and spurious perform ance. it can be shown that 19-bit phase resolution is sufficient to yield 14-bit am plitude resolution with an error of less than ? lsb. the decision to truncate at 19 bits of phase guarantees the phase error of the cos(x) block to be less than the phase error associated with the amplitude resolution of the 14-bit dac. clock input the AD9951 supports various clock m e thodologies. support for differe ntial or single-ended input clocks, enabling of an on-chip oscillator a nd/or phase-locked loop (pll) multiplier are all controlled via user program m a ble bits. the ad 9951 m a y be configured in one of six operating m odes to generate the system clock. the m ode s are configured using the clkmodeselect pin, cfr2<0>, and cfr2<7:3>. connecting the exte rnal pin clkmodeselect to logic high enables the on-chip crystal oscillator circuit. with th e on-chip oscillator enabled, users of the AD9951 connect an external crystal to the refclk and refclkb inputs to produce a low frequency reference clock in the range of 20-30mhz. the signa l generated by the oscillator is buffered before it is delivered to the rest of th e chip. this buffered signal is available via the crystal out pin. bit cfr2<0> can be used to enable or disable the buffer, turning on or off the system clock. the oscillator itself is not powered down in order to avoid long start-up times associated with turning on a crystal oscillator. writing bit cfr2<1> to l ogic high enables the crystal oscillator output buffer. logic low at cfr2<1> disables the oscillator output buffer. connecting clkmodeselect to logic low disables the on-chip oscillator and the oscillator output buffer. with the oscillator disabl ed an external oscillator must provide the refclk and/or refclkb signals. for differential operation these pins are driven with com p lem e ntary signals. for single-ended operation a 0.1uf capacitor should be connected between the unused pin and the positive power supply. with the capacitor in place th e clock input pin bias voltage is 1.35v. in addition, the pll may be used to multiply the re ference frequency by an integer value in the range of the 4 to 20. the modes of operation are summarized in the table below. please note the pll multiplier is controlled via the cfr2<7:3> bits, i ndependently of the cfr2<0> bit. rev . p r a 1/31/03 page 11 analog devices , inc.
preliminary technical data AD9951 c l k m o d e s e l e c t c f r 2 < 0 > c f r 2 < 7 : 3 > s y s t e m clock frequency range (mhz) high low 3 < m < 21 f clk = f osc x m 80 < f clk < 400 high low m < 4 or m > 20 f clk = f osc 20 < f clk < 30 h i g h h i g h x f clk = 0 f clk = 0 low x 3 < m < 21 f clk = f ref x m 80 < f clk < 400 low x m < 4 or m > 20 f clk = f ref 5 < f clk < 400 table 2 clock input modes of operation phase locked loop (pll) the pll is required to facilitate multiplication of the refclk frequency. control of the pll is accomplished by programming the 5-bit refclk mu ltiplier portion of control function register #2, bits <7:3>. when programmed for values ranging from 04h ? 14h (4-20 decimal), the pll multiplies the refclk input frequency by the co rresponding decim a l value. th e m a xim u m output frequency of the pll is restricted to 400mhz, however. whenev er the pll value is changed, the user should be aware that time must be allocated to a llow the pll to lock (approximately 1ms). the pll is bypassed by program m i ng a value outsi de the range of 4-20 (decim al). when bypassed, the pll is shut down to conserve power. dac output the AD9951 incorporates an integrated 14-bit current output dac. two com p lem e ntary outputs provide a com b ined full-scale output current (i out ). differential outputs reduce the am ount of com m on-m ode noise that m i ght be present at the dac output, offering the advantage of an increased signal-to-noise ratio. the full-scale current is controlled by m e ans of an external resistor (r set ) connected between the dac_rset pin a nd the dac ground (agnd_dac). the full-scale current is proportional to the resistor value as follows: r set = 39.19/i out the m a xim u m full-scale output current of the co m b ined dac outputs is , but lim iting the output to y provides the best spurious-free-dyna mic-range (sfdr) performance. the dac output compliance range is . voltages develope d beyond this range will cause excessive dac distortion and could potentially dam a ge the dac out put circuitry. proper a ttention should be paid to the load termination to keep the output voltage w ithin this compliance range. rev . p r a 1/31/03 page 12 analog devices , inc.
preliminary technical data AD9951 serial io port the AD9951 serial port is a flexible, synchronous serial com m unications port allowing easy interface to many industry standard micro-controlle rs and microprocessors. the serial i/o port is com p atible with m o st synchronous transfer fo rm ats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. the interface allows read/write access to all regist ers that configure the AD9951. msb first or lsb first transfer formats are supported. in add ition, the AD9951?s serial interface port can be configured as a single pin i/o (sdio), which allows a two-wire interface or two unidirectional pins for in/out (sdio/sdo), which enables a three wire interface. two optional pins (iosync and csb) enable greater flexibility for system design-in of the AD9951. register maps and descriptions the register map is listed in the following tables . the serial address numbers associated with each of the registers are shown in hexadecimal fo rmat. angle brackets <> are used to reference specific bits or ranges of bits. for example, <3 > designates bit 3 while <7:3> designates the range of bits from 7 down to 3, inclusive. rev . p r a 1/31/03 page 13 analog devices , inc.
preliminary technical data AD9951 AD9951 register map regis t er name (s erial addr e ss) bit range (i n t ern al addr e ss) (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value <7:0> (00h ) digital powe r down open dac power down clock input power dwn external powe r down mode open sy nc clk out disable open 00h <15:8> (01h) open open autoclr p h as e accum enable sine output o p en clear p h as e accum . sdio input only ls b first 00h <23:16> (02h) autom a tic sy nc enable software manual sy nc open amplitude dither enable p h as e dither en<3> p h as e dither en<2> p h as e dither en<1> p h as e dither en<0> 00h control function register #1 ( cfr1 ) (00h) <31:24> (03h) open open not used load arr @fud output s h aped key i ng enable auto output s h aped key i ng 00h <7:0> (04h) refclk multiplier 00h or 01h or 02h or 03h: by pass multiplier 04h ?14h: 4x ? 20x m u ltiplication vco gain charge pump control <1:0> 00h <15:8> (05h) not used high s p eed sy nc enable hardware manual sy nc enable cry s tal out pin active dac prime data disable 00h control function register #2 (cfr2) (01h) <23:16> (06h) not used 00h <7:0> (07h) am plitude s cale f actor regis t er <7:0> - amplitude s cale f actor ( asf ) (02h) <15:8> (08h) a u to ram p rate speed control <1:0> amplitude scale factor register <13:8> - amplitude ramp rate (arr) (03h) <7:0> (09h) am plitude ram p rate register <7:0> - <7:0> (0ah) frequency tuning word #0 <7:0> 00h <15:8> (0bh) frequency tuning word #0 <15:8> 00h <23:16> (0ch) frequency tuning word #0 <23:16> 00h frequency tuning word ( ftw0 ) (04h) <31:24> (0dh) frequency tuning word #0 <31:24> 00h <7:0> (0eh) p h as e offs et w o rd #0 <7:0> 00h p h as e offset word ( pow0 ) (05h) <15:8> (0fh) open<1:0> phase offset word #0 <13:8> 00h rev . p r a 1/31/03 page 14 analog devices , inc.
preliminary technical data AD9951 control register bit descriptions control functi on regi ster #1 (cfr1) the cfr1 is used to control the various func tions, features, and m odes of the AD9951. the functionality of each bit is detailed below. cfr1<26>: amplitude ramp rate load control bit. when cfr1<26> = 0 (default) , the am plitude ram p rate tim er is loaded only upon tim eout (tim er ==1) and is not loaded due to an i/o update input signal. when cfr1<26> = 1, the am plitude ram p rate tim er is loaded upon tim eout (tim er ==1) or at the tim e of an i/o update input signal. cfr1<25>: shaped on-off keying enable bit. when cfr1<25> = 0 (d efa u lt,) shaped on-off keying is bypassed. when cfr1<25> = 1, shaped on-off ke ying is enabled. when enabled, cfr1<24> controls the m ode of operation for this function. cfr1<24>: auto shaped on-off keying enable bit (only valid when cfr1<25> is active high). when cfr1<24> = 0 (default). when cfr1<25> is active, a logic 0 on cfr1<24> enables the manual shaped on -off keying operation. see the shaped on-off keying section of this document for details. when cfr1<24> = 1, if cfr1<25> is ac tive, a logic 1 on cfr1<24> enables the auto shaped on-off keying operation. see the shaped on-off keying section of this document for details. cfr1<23>: autom a tic synchronization mode. when cfr1<23> = 0 (default), the automatic synchronization of multiple AD9951s feature is inactive. when cfr1<23> = 1, the autom a tic sync hronization feature is active. see the synchroniz ing multiple AD9951s section of this document for details. rev . p r a 1/31/03 page 15 analog devices , inc.
preliminary technical data AD9951 cfr1<22>: software controlled manua l synchronization mode. when cfr1<22> = 0 (default), the m a nual synchronization feature is inactive. when cfr1<22> = 1, the software cont rolled m a nual synchronization feature is executed. the sync_clk rising edge is advanced by one sysclk cycle and this bit is cleared. to advance the rising edge mu ltiple times, this bit needs to be set for each advance. see the synchroniz ing multiple AD9951s section of this docum ent . cfr1<20>: amplitude dither enable bit. when cfr1<20> = 0 (default) , am plitude dithering is disabled. when cfr1<20> = 1, am plitude dithering is enabled. cfr1<19>: phase bit <16> dither enable bit. when cfr1<19> = 0 (default) , phase dithering for truncated phase words, bit 16 of <31:13>, is disabled. when cfr1<19> = 1, phase dithering for truncated phase words, bit 16 of <31:13>, is enabled. cfr1<18>: phase bit <15> dither enable bit. when cfr1<18> = 0 (default) , phase dithering for truncated phase words, bit 15 of <31:13>, is disabled. when cfr1<18> = 1, phase dithering for truncated phase words, bit 15 of <31:13>, is enabled. cfr1<17>: phase bit <14> dither enable bit. when cfr1<17> = 0 (default) , phase dithering for truncated phase words, bit 14 of <31:13>, is disabled. when cfr1<17> = 1, phase dithering for truncated phase words, bit 14 of <31:13>, is enabled. rev . p r a 1/31/03 page 16 analog devices , inc.
preliminary technical data AD9951 cfr1<16>: phase bit <13> dither enable bit. when cfr1<16> = 0 (default) , phase dithering for truncated phase words, bit 13 of <31:13>, is disabled. when cfr1<16> = 1, phase dithering for truncated phase words, bit 13 of <31:13>, is enabled. sequence indicator. cfr1<13>: autoclear phase accumulator bit. when cfr1<13> = 0 (default) , a new frequency tuning word is applied to the inputs of the phase accumulator, but not loaded into th e accumulator. when cfr1<13> = 1, this bit autom a tically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the i/o update sequence indicator. cfr1<12>: sine/cosine select bit. when cfr1<12> = 0 (default) , the angle-to-am p litude conversion logic em ploys a cosine function. when cfr1<12> = 1, the angle-to-am p litude conversion logic em ploys a sine function. cfr1<10>: clear phase accumulator. when cfr1<10> = 0 (default) , the phase accum ulator functions as norm a l. when cfr1<10> = 1, the phase accum u la tor m e m o ry elem ents are asynchronously cleared and held clear until this bit is set back to zero. cfr1<9>: sdio input only. when cfr1<9> = 0 ( default ), the sdio pin has bi-directional operation (2-wire serial program m i ng m ode). when cfr1<9> = 1, the serial data i/o pin (sdio) is configured as an input only pin (3-wire serial program m i ng m ode). rev . p r a 1/31/03 page 17 analog devices , inc.
preliminary technical data AD9951 cfr1<8>: lsb first. when cfr1<8> = 0 ( default ), msb first format is active. when cfr1<8> = 1, the serial interface a ccepts serial data in lsb first format. cfr1<7>: digital power down bit. when cfr1<7> = 0 ( default ), all digital functions and clocks are active. when cfr1<7> = 1, all non-io digital f unctionality is suspended and all heavily loaded clocks are stopped. this bit is inte nded to lower the digital power to nearly zero, without shutting down the pll cl ock multiplier function or the dac. cfr1<5>: dac power down bit. when cfr1<5> = 0 ( default ), the dac is enabled for operation. when cfr1<5> = 1, the dac is disabled and is in its lowest power dissipation state. cfr1<4>: clock input power down bit. when cfr1<4> = 0 ( default ), the clock input circuitry is enabled for operation. when cfr1<4> = 1, the clock input circuitr y is disabled and the device is in its lowest power dissipation state. cfr1<3>: external power down mode. when cfr1<3> = 0 (default) the external power down mode selected is the ?fast recovery power down? m ode. in this m ode , when the pwrdwnctl input pin is high, the digital logic and the dac digital logic are powered down. the dac bias circuitry, pll, oscillator, and clock i nput circuitry is not powered down. when cfr1<3> = 1, the external power down m ode selected is the ?full power down? m ode. in this m ode, when the pwrdwn ctl input pin is high, all functions are powered down. this includes the dac and pll, which take a significant am ount of tim e to power up. cfr1<1>: syncclk disable bit. when cfr1<1> = 0 (default) , the syncclk pin is active. rev . p r a 1/31/03 page 18 analog devices , inc.
preliminary technical data AD9951 when cfr1<1> = 1, the syncclk pin assum e s a static logic 0 state (disabled). in this state the pin drive logic is shut dow n to keep noise generated by the digital circuitry at a m i nim u m . however, the synchronization circuitry rem a ins active (internally) to maintain normal device timing. cfr1<0>: not used. leave at 0. note: assertion of this bit m a y cause th e syncclk pin to m o m e ntarily stop generating a sync cloc k signal. the device will not be oper a tional dur ing the r e - s y n chr onization per i od. control functi on regi ster #2 (cfr2) the cfr2 is com p rised of three bytes located in parallel addresses 06h-04h. the cfr2 is used to control the various functions, fe atures, and m odes of the AD9951, prim arily related to the analog sections of the chip. all bits of the cfr2 will be routed direc tly to the analog section of the AD9951 as a single 24-bit bus labeled cfr2<23:0>. cfr2<15:12>: not used. cfr2<11>: high speed sync enable bit. when cfr2<11> = 0 (default) the high speed sync enhancement is off. when cfr2<11> = 1, the high speed sync enhancem ent is on. see the synchroniz ing multiple AD9951s section of this document for details. cfr2<10>: hardware manual sync enable bit. when cfr2<10> = 0 (default) the hardware manual sync function is off. when cfr2<11> = 1, the hardware manual sync function is enabled. while this bit is set, a rising edge on the sync_in pin will cause th e device to advance the sync_clk rising edge by one refclk cycle. unlike the software manual sync enable bit, this bit does not self-clear. once the hardware manual sync mode is enabled, it will stay enabled until this bit is cleared. see the synchroniz ing multiple AD9951s section of this document for details. cfr2<9>: crystal out enable bit. when cfr2<9> = 0 (default) the crystal out pin is inactive. when cfr2<9> = 1, the crystal out pin is ac tive. when active, the crystal oscillator circuitry output drives the crystal out pin, which can be connected to other devices to produce a reference frequency. rev . p r a 1/31/03 page 19 analog devices , inc.
preliminary technical data AD9951 cfr2<8>: dac prim e data disable bit. when cfr2<8> = 0 ( default ), the dac prime data is enabled for operation. when cfr2<8> = 1, the dac prime data is not generated and these outputs rem a in logic zeros. cfr2<7:3>: reference clock multiplier control bits. see the phase locked loop (pll) section of this document for details. cfr2<2>: vco gain control bit. this bit is us ed to control the gain setting on the vco. cfr<1:0>: charge pump gain control bits. these bits are used to control the gain setting on the charge pum p. other register descriptions amplitude scale factor (asf) the asf register stores the 2-bit auto ramp rate speed value asf<15:14> and the 14-bit am plitude scale factor asf<13:0> used in the output shaped keying (osk) operation. in auto osk operation, that is cfr1<24> = 1, asf < 15:14> tells the osk block how m a ny am plitude steps to take for each incremen t or decrement. asf<13:0> sets the maximum value achievable by the osk internal multiplier. in manual osk mode , that is cfr1<24>=0, asf<15:14> have no affect. asf <13:0> provide the out put scale factor directly. if the osk enable bit is cleared, cfr1<25>=0, this register has no affect on device operation. amplitude ramp rate (arr) the arr register stores the 8-bit am plitude ram p rate used in the auto osk mode, that is cfr1<25>=1, cfr<24>=1. this register program s the rate the am plitude scale factor counter increments or decrements. in the osk is set to manual mode, cfr1<25>=1 cfr<24>=0, or if osk enable is cleared cfr1< 25>=0, this register has no affect on device operation. frequency tuning word 0 (ftw0) the frequency tuning word is a 32-bit register that controls the rate of accumulation in the phase accumulator of the dds core. its specific role is dependent on th e device mode of operation. phase offset word (pow) the phase offset word is a 14-bit register that st ores a phase offset value. this offset value is added to the output of the phase accumulator to o ffset the current phase of the output signal. the exact value of phase offset is given by the following form ula: q ? 1 ? ) 360 * 2 14 pow rev . p r a 1/31/03 page 20 analog devices , inc. mode of operation
preliminary technical data AD9951 single tone mode in single tone m ode, the dds core uses a single t uning word. whatever value is stored in ftw0 is supplied to the phase accumulator. this value ca n only be changed static ally, which is done by writing a new value to ftw0 and issuing an i/ o update. phase adjustm e nt is possible through the phase offset register. c ont i nuous c l ear and ?c l e ar and rel e ase? phase accumul a t o r c l ear funct i ons the AD9951 allows for a program m a ble continuous zer oing of the phase accum u lator as well as a ?clear and release?, or automatic zeroing function. each feature is individually controlled via bits the cfr1. cfr1<13> is the auto matic clear phase accumulator b it. cfr1<10> clears the phase accumulator. c ont i nuous c l ear bi t s the continuous clear bits are sim p ly static c ontrol signals that, when active high, hold the respective accumulator at zero for th e entire time the bit is active. when the bit goes low, inactive, the accumulator is allowed to operate. c l ear and rel e ase f unct i on the auto clear phase accum u la tor, when set, clears and releases the phase accum u lator upon receiving an i/o update. the automatic clearing f unction is repeated for every subsequent i/o update until the appropriate auto-cl ear control bit is cleared. programming AD9951 features phase offset control a 14-bit phase-offset ( t ) m a y be added to the output of the phase accum u lator by m eans of the control registers. this feature provides the user with two different m e thods of phase control. the first m e thod is a static phase adjustm e nt, where a fixed phase-offset is loaded into the appropriate phase-offset register a nd left unchanged. the result is th at the output signal is offset by a constant angle relative to the nominal signal. th is allows the user to phase align the dds output with some external signal, if necessary. the second m e thod of phase control is where the us er regularly updates the phase-offset register via the i/o port. by properly m odifying the pha se-offset as a function of time, the user can im plem ent a phase m odulated output signal. ho wever, both the speed of the i/o port and the frequency of sysclk lim it the rate at whic h phase m odulation can be perform ed. phase/amplitude dithering rev . p r a 1/31/03 page 21 analog devices , inc.
preliminary technical data AD9951 the AD9951 dds core includes optional phase and/ or amplitude dithering controlled via the cfr1<20:16> bits. phase dithering is the random ization of the state of the least significant bits of each phase word. phase dithering reduces spurious signal strengt h caused by phase truncation by spreading the spurious energy over the entire spectrum . the downsid e to dithering is a rise in the noise floor. amplitude dithering is similar, except it a ffects the output signal routed to the dac. phase dithering is independently controlled on the four least significant bits of the phase word routed to the angle rotation function. that is, any or all of the phase word four least significant bits m a y be dithered or not dithered, controlled by th e user via the serial port. specifically, the cfr1<19> bit controls the phase dithering enab le function of the phase word <16> bit. the cfr1<18> bit controls the phase dithering enab le function of the phase word <15> bit. the cfr1<17> bit controls the phase dithering enab le function of the phase word <14> bit. the cfr1<16> bit controls the phase dithering enable function of the phase word <13> bit. this enable function is such that if the bit is high, dithering is enabled. if the bit is low, dithering is not enabled. am plitude dithering uses one control bit to enable or disable dithering. if the am plitude dither enable bit (cfr1<20>) is logic 0, no am plitude dithering is enabled and the data from the dds core is passed unchanged. when high, amplitude dithering is enabled. shaped on-off keying general description: the shaped on-off keying function of the AD9951 allows the user to control the ram p -up and ram p -down tim e of an ? on-off? em ission from the dac. this function is used in ?burst transm issions? of digital data to reduce the adverse spectral im pact of short, abrupt bursts of data. auto and manual shaped on-off keying m odes ar e supported. the auto m ode generates a linear scale factor at a rate determined by the am plitude ram p rate (arr) register controlled by an external pin (osk). manual mode allows the us er to directly control the output amplitude by writing the scale factor value into the amp litude scale factor (asf) register (asf). the shaped on-off keying function m a y be bypassed (disabled) by clearing the osk enable bit (cfr1<25>=0). the m odes are controlled by two bits located in th e m o st significant byte of the control function register (cfr). cfr1<25> is the shaped on-off ke ying enable bit. when cfr1<25> is set, the output scaling function is enable d; cfr1<25> bypasses the function. cfr1<24> is the internal shaped on-off keying active bit. wh en cfr1<24> is set, internal shaped on-off keying m ode is active; cfr1<24> cleared is ex ternal shaped on-off keying mode active. cfr1<24> is a ?don?t care? if the shaped on-off keyi ng enable bit (cfr1<25>) is cleared. the power up condition is rev . p r a 1/31/03 page 22 analog devices , inc.
preliminary technical data AD9951 shaped on-off keying disabled (cfr1<25> = 0). figure c below shows the block diagram of the osk circuitry. co s(x ) dd s co re to d a c osk en able cfr<25> 0 1 amplit u de scale f a ct or r e gist er (asf ) 0 1 0 0 1 out hold up /dn osk pi n a m plitud e ramp rate registe r (arr ) loa d data en load os k timer cfr1<26> sy nc clo c k clock inc/dec ena b le ra mp rat e time r aut o scale factor ge nerator auto o s k ena b le cfr<24> figure c. on-off shaped keying, block diagram auto shaped on-off keying m ode operation: the auto shaped on-off keying mode is active wh en cfr1<25> and cfr1<24> are set. when auto shaped on-off keying m ode is enabled, a si ngle scale factor is internally generated and applied to the multiplier input for scaling the output of the dds core block (see figure 9 above). the scale factor is the output of a 14-bit counter which increm ents/decrem e nts at a rate determ ined by the contents of the 8-bit output ram p rate regist er. the scale factor increases if the osk pin is high, decreases if the pin is low. the scale factor is an unsigned value such that all zeros multiplies the dds core output by 0 (decimal) and 3fffh multiplies the dds core output by 16383 decimal. for those users who use the full am plitude (14-bits ) but need fast ramp rates, the internally generated scale factor step size is controlled vi a the asf<15:14> bits. the table below describes the increment/decrement step size of the internally generated scale factor per the asf<15:14> bits. rev . p r a 1/31/03 page 23 analog devices , inc.
preliminary technical data AD9951 asf<15:14> (binary) increment/decrement size 0 0 1 0 1 2 1 0 4 1 1 8 table 5 auto-scale factor internal step size a special feature of this mode is that the m a xim u m output am plitude allowed is lim ited by the contents of the am plitude scale factor register. th is allows the user to ra mp to a value less than full scale. osk ram p rate tim e r the osk ram p rate tim er is a loadable down count er, which generates the clock signal to the 14-bit counter that generates the internal scale factor. th e ram p rate tim er is load ed with the value of the asfr every tim e the counter reaches 1 (decim a l). this load and count down operation continues for as long as the tim er is enabled unless the tim er is forced to load before reaching a count of 1. if the load osk tim e r bit (cfr1<26>) is set, th e ram p rate tim er is loaded upon an i/o update or upon reaching a value of 1. the ramp timer can be loaded before reaching a count of 1 by three m e thods. method one is by changing the osk input pin. when the osk input pin changes state the asfr value is loaded into the ramp rate timer, which then proceeds to count down as normal. the second m e thod in which the sweep ram p rate tim er can be loaded before reaching a count of 1 is if the load osk timer bit (cfr1<26>) bit is set and an i/o update is issued. the last m e thod in which the sweep ram p rate tim er can be loaded before reaching a count of 1 is when going from the inactive auto shaped on-off keying m ode to the active auto shaped on-off keying mode. that is, when the sweep enable bit is being set. external shaped on-off keying m ode operation: the external shaped on-off keying mode is enabled by writing cfr1<25> to a logic 1 and writing cfr1<24> to a logic 0. when configured for external shaped on -off keying, the content of the asfr becomes the scale factor for the da ta path. the scale factors are synchronized to dds_clock via the i/o update functionality. rev . p r a 1/31/03 page 24 analog devices , inc.
preliminary technical data AD9951 sy nchronization; register updates (i/o update) functionality of the syncclk and i/o update data into the AD9951 is synchronous to the syncclk pin. that is, the i/o update pin is sam p led on the rising edge of the s yncclk clock provided by the AD9951. as shown in the figure d, sysclk is fed to a divide-by-4 frequency divi der to produce sync_clk which is also provided to the user on the syncclk pin. this enables synchronization of external hardware with the AD9951?s internal dds clock. this is accom plished by forcing any external hardware to obtain its tim ing from syncclk. exte rnal hardware that is tim ed using the syncclk signal can then be used to provide the i/o update (frequency update) signal to the AD9951. the i/o update signal coupled with syncclk is used to transfer internal buffer register contents into the control registers of the device. the com b ination of the syncclk and i/o update pins provides the user with constant latency relative to sysclk and also ensures phase continuity of the analog output signal when a new tuning word or phase offset value is asserted. figure e dem onstrates an i/o update tim ing cycle and synchronization. notes to synchronization logic: 1) the i/o update signal is edge detected to generate a single rising edge clock signal that drives the register bank flops. the i/o update signal has no constraints on duty cycle. the minimum low time on i/o up date is one sync_clk clock cycle. 2) the i/o update pin is setup and held ar ound the rising edge of sync_clk and has zero hold tim e and 10ns setup tim e. rev . p r a 1/31/03 page 25 analog devices , inc.
preliminary technical data AD9951 0 1 0 sy nc clk disa ble d q d q d q os k p r ofile<1:0> i/o upda t e e dge detectio n lo gic synccl k gating register me m o ry i/o buff er latches sc lk sdi cs to core logic sy sclk 4 figure d- i/o synchroniz ation block diagram data [1] data[ 1 ] d a t a(2) data (2) d ata(3) dat a ( 3 ) ab sy sc l k sy nclk i/o update data in registe r s data in i/o b u ffers t he device regist ers an i / o u pdate at point a. t h e data is t r an f e rred f r o m the asynch ronously load ed i / o buf fers at p o int b. figure e - i/o synchroniz ation timing diagram rev . p r a 1/31/03 page 26 analog devices , inc.
preliminary technical data AD9951 sy nchronizing multiple AD9951s the AD9951 product allows easy sync hronization of multiple AD9951s. there are three modes of synchronization available to the user: an autom a tic synchronization m ode; a software controlled m a nual synchronization m ode; and a hardware controlled m a nual synchronization m ode. in all cases, when a user wants to synchronize two or m o re devices, the following considerations m u st be observed. first, all units must share a common cl ock source. trace lengths and path im pedance of the clock tree m u st be designed to keep the phase delay of the different clock branches as closely m a tched as possible. second, the i/o update signa l?s rising edge m u st be provided synchronously to all devices in the system . finally, regardless of the internal synchronization m e thod used, the dvdd_i/o supply should be set to 3.3v for all devices that are to be synchronized. avdd and dvdd should be left at 1.8v. in autom a tic synchronization m ode, one device is chosen as a master, the other device(s) will be slaved to this master. when configured in this mode, all the slaves will automatically synchronize their internal clocks to the sync_clk output signal of the m a ster device. to enter autom a tic synchronization m ode, set the slav e device?s autom a tic synchronization bit (cfr1<23>=1). connect the sync_in input(s) to the m a ster sync_clk output. the slave device will continuously update the pha se relationship of its sync_clk until it is in phase with the sync_in input, which is the sync_clk of the m a ster device. when attem p ting to synchronize devices running at sysclk speeds beyond 250msps, th e high-speed sync enhancem ent enable bit should be set (cfr2<11>=1). in software m a nual synchronization m ode, the user forces the device to advance the sync_clk rising edge one sysclk cycle (1/4 sync_clk period). to activate the m a nual synchronization m ode, set the slave device?s so ftware m a nual synchronization bit (cfr1<22> =1). the bit (cfr1<22>) will be immediately cleared. to advance the rising edge of the sync_clk multiple times, this bit will n eed to be set multiple times. in hardware m a nual synchronization m ode, the s ync_in input pin is configured such that it will now advance the rising edge of the sync_clk signal each time the device detects a rising edge on the sync_in pin. to put the device into hardware m a nual synchronization m ode, set the hardware m a nual synchronization bit (cfr2<10>=1 ). unlike the software m a nual synchronization bit, this bit does not self-clear. once the hard ware m a nual synchronization m ode is enabled, all rising edges detected on the sync_in input will caus e the device to advance the rising edge of the sync_clk by one sysclk cycle until this enable bit is cleared (cfr2<10=0). using a single cry s tal to dri ve multiple AD9951 clock inputs the AD9951 crystal oscillator output signal is availa ble on the crystalout pin, enabling one crystal to drive multiple AD9951s. in order to drive mu ltiple AD9951s with one crystal, the crystalout pin of the AD9951 using the external crystal shoul d be connected to the refclk input of the other AD9951. the crystalout pin is static until the cfr2<1> bit is set, enabling the output. the drive strength of the crystalout pin is typically very low, so this signal should be buffered prior to using it to drive any loads. rev . p r a 1/31/03 page 27 analog devices , inc.
preliminary technical data AD9951 serial port operation with the AD9951, the instruction by te specifies read/write operation and register address. serial operations on the AD9951 occur only at the register level, not the byte level. for the AD9951, the serial port controller recognizes the instruction by te register address and autom a tically generates the proper register byte address. in addition, the cont roller expects that all bytes of that register will be accessed. it is a requirement that all bytes of a register be accessed during serial i/o operations, with one exception. the syncio function can be used to abort an io operation thereby allowing less than all bytes to be accessed. there are two phases to a com m unication cycle with the AD9951. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9951, coincident with the first eight sclk rising edges. the instruction byte provides the AD9951 serial port controller with inform ation regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcom ing data tr ansfer is read or write and the serial address of the register being accessed. [note ? the serial address of the register being accessed is not the same address as the bytes to be written. see th e example operation section below for details]. the first eight sclk rising edges of each com m uni cation cycle are used to write the instruction byte into the AD9951. the rem a ining sclk edges are for phase 2 of the com m unication cycle. phase 2 is the actual data transfer between th e AD9951 and the system controller. the num ber of bytes transferred during phase 2 of the com m unica tion cycle is a function of the register being accessed. for example, when accessing the control f unction register 2, which is three bytes wide, phase 2 requires that three bytes be transferred. if accessing the frequency tuning word, which is four bytes wide, phase 2 requires th at four bytes be transferred. af ter transferring all data bytes per the instruction, the communi cation cycle is completed. at the com p letion of any com m unication cycle, th e AD9951 serial port controller expects the next 8 rising sclk edges to be the instruction byte of the next com m unication cycle.all data input to the AD9951 is registered on the rising edge of sc lk. all data is driven out of the AD9951 on the falling edge of sclk. figures 34 - 37 are useful in understanding the general operation of the AD9951 serial port. rev . p r a 1/31/03 page 28 analog devices , inc.
preliminary technical data AD9951 instruction by te the instruction byte contains the following in form ation as shown in the table below: instruction byte information m s b d 6 d 5 d 4 d 3 d 2 d 1 l s b r / w b x x a 4 a 3 a 2 a 1 a 0 table 6 instruction byte r/-wb?bit 7 of the instruction byte determines wh ether a read or write data transfer will occur after the instruction byte write. logic high indicat es read operation. logic zero indicates a write operation. rev . p r a 1/31/03 page 29 analog devices , inc.
preliminary technical data AD9951 x, x?bits 6 and 5 of the instruction byte are don?t care. a4, a3, a2, a1, a0?bits 4, 3, 2, 1, 0 of the in struction byte determ ine which register is accessed during the data transfer portion of the com m unications cycle. seri al int e rf ace port pi n descri pt i on sclk ? serial clock. the serial clock pin is us ed to synchronize data to and from the AD9951 and to run the internal state machin es. sclk m a xim u m frequency is 25 mhz. csb ? chip select bar. active low input that allo ws m o re than one device on the sam e serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cy cle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio ? serial data i/o. data is always written into the AD9951 on this pin. however, this pin can be used as a bi-directional data line. bit 7 of register address 0h contro ls the configuration of this pin. the default is logic zero, which c onfigures the sdio pin as bi-directional. sdo ? serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case wher e the AD9951 operates in a single bi-directional i/o m ode, this pin does not output data and is set to a high im pedance state. syncio ? synchronizes the i/o port state m a chines w ithout affecting the addressable registers contents. an active high input on the sync i/o pin causes the current com m unication cycle to abort. after sync i/o returns low (logic 0) another com m unication cycle m a y begin, starting with the instruction byte write. msb/lsb transfers the AD9951 serial port can support both m o st signifi cant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the control register 00h<8> bit. the default value of control register 00h<8> is low (m sb first). when control register 00h<8> is set high, the AD9951 serial port is in lsb first form at. the instruction byte must be written in the form at indicated by control register 00h<8>. that is, if the AD9951 is in lsb first m ode, the instruction byte must be written from least significant bit to most significant bit. for msb first operation, the serial port controller will generate the most significant byte (of the specified register) address first followed by the ne xt lesser significant byte addresses until the io operation is complete. all data written to (read from) the AD9951 must be (will be) in msb first order. if the lsb mode is active, the serial port controller will generate the least significant byte address first followed by the next greater signi ficant byte addresses until the io operation is complete. all data written to (read from) the AD9951 must be (will be) in lsb first order. rev . p r a 1/31/03 page 30 analog devices , inc.
preliminary technical data AD9951 exampl e operat i on to write the am plitude scale factor register in msb first form at apply an instruction byte of 02h (serial address is 00010(b)). from this instruction, the internal controller w ill generate an internal byte address of 07h (see the register map) for the fi rst data byte written and an internal address of 08h for the next byte written. since the amplitude sc ale factor register is two bytes wide, this ends the communication cycle. to write the am plitude scale factor register in lsb first form at apply an instruction byte of 40h. from this instruction, the intern al controller will generate an internal byte address of 07h (see the register map) for the first data byte written and an internal address of 08h for the next byte written. since the amplitude scale factor register is tw o bytes wide, this ends the com m unication cycle. n o t e s on seri al port operat i on 1) the AD9951 serial port configuration bits resi de in bits 8 and 9 of cfr1 (address 00h). the configuration changes immediat ely upon writing to this register. for multi-byte transfers, writing to this register m a y occur during the m i ddle of a com m unication cycle. care m u st be taken to compensate for this new confi guration for the rem a inder of the current communication cycle. 2) the system m u st m a intain synchronization with the AD9951 or the internal control logic will not be able to recognize further instruc tions. for example, if the system sends an instruction byte that describes writing a 2-byte register, then pulses the sclk pin for a 3- byte write (24 additional sclk rising edges), co m m unication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle will properly write the first two data bytes into the AD9951, but the next ei ght rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous com m unication cycle. in the case where synchronization is lost between the system and the AD9951, the sync i/o pin provides a means to re-establish synchronizati on without re-initializing the entire chip. the sync i/o pin enables the user to reset the AD9951 state machine to accept the next eight sclk rising edges to be coincident with the instruction phase of a new com m unication cycle. by applying and rem oving a ?high? signal to the sync i/o pin, the AD9951 is set to once again begin perform ing the com m unication cycle in synchronization with the system . any information that had been written to the AD9951 registers during a valid communication cycle prior to loss of synchronization will remain intact. pow e r dow n functions of the AD9951 the AD9951 supports an externally controlled, or hardware, power down feature as well as the m o re com m on software program m a ble power down bits found in previous adi dds products. the software control power down allows the dac, p ll, input clock circuitry and the digital logic to be individually power down via unique contro l bits (cfr1<7:4>). these bits are not active when the externally controlled power down pin (pwrdwnctl) is high. external power down control is supported on the AD9951 via the pwrdwnc tl input pin. when the pwrdwnctl input pin rev . p r a 1/31/03 page 31 analog devices , inc.
preliminary technical data AD9951 is high, the AD9951 will enter a power down m ode based on the cfr1<3> bit. when the pwrdwnctl input pin is low, the extern al power down control is inactive. when the cfr1<3> bit is zero, and the pwrdwnctl input pin is high, the AD9951 is put into a ?fast recovery power down? m ode. in this m ode , the digital logic and the dac digital logic are powered down. the dac bias circuitry, pll, osc illator, and clock input circuitry is not powered down. when the cfr1<3> bit is high, and the pwrdwnc tl input pin is high, the AD9951 is put into the ?full power down? m ode. in this m ode, all func tions are powered down. this includes the dac and pll, which take a significant am ount of tim e to power up. when the pwrdwnctl input pin is high, the i ndividual power down bits (cfr1<7>, <5:4>) are invalid (don?t care) and are unused. when the pwr dwnctl input pin is low, the individual power down bits control the power down m odes of operation. note ? the power down signals are all designed such that a logic 1 indicates the low power m ode and a logic zero indicates the active, or powered up m ode. the table below indicates the logic level for e ach power down bit that drives out of the AD9951 core logic to the analog section and the digital cloc k generation section of the chip for the external power down operation. control mode active description pwrdwnctl = 0 cfr1<3> don?t care software control digital power down = cfr1<7> dac power down = cfr1<5> input clock power down = cfr1<4> pwrdwnctl = 1 cfr1<3> = 0 external control, fast recovery power down m ode digital power down = 1?b1; dac power down = 1?b0; input clock power down = 1?b0; pwrdwnctl = 1 cfr1<3> = 1 external control, full power down m ode digital power down = 1?b1; dac power down = 1?b1; input clock power down = 1?b1; table 7 power down control functions digital and input clock pow e r dow n the digital power down bit stops all clocks associat ed with the digital sec tion of the chip. this includes the syncclock signal. it?s im portant to note that when the syncclock is stopped, the io port cannot be updated. the figure shown below s hows the logical functionality required of the digital power down bit. the power down bit can be disabled (power back on) without the need for syncclock being activated. rev . p r a 1/31/03 page 32 analog devices , inc.
preliminary technical data AD9951 AD9951 application suggestions a d 9951 lpf refclk rf /if i nput m odulated/ demodulat ed s i gnal figure f s y nthesized l.o fo r u p conversion/ d o w n c onversion a d 9951 filter phase comparator loop filter vco tuning wo r d figure g digit a lly program mable ?divi d e-by-n? function in pll re f s i gnal rev . p r a 1/31/03 page 33 analog devices , inc.
preliminary technical data AD9951 rev . p r a 1/31/03 page 34 analog devices , inc. AD9951 d d s lpf iout freque ncy t u ning word crysta l out sy nc out pha s e offset word 1 sa w crystal a d 9951 dds lpf iout freque ncy t u ning word sync in pha s e offse t wo rd 2 re f c l k re f c l k refcl k i baseba nd q b a se band rf out figure h tw o a d 9951s sync hr onized to provide i & q c a rriers w i th independent phas e of fset s f o r n u lling

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